The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2024
Filed:
Nov. 15, 2021
Texas Instruments Incorporated, Dallas, TX (US);
Rafael Jose Lizares Guevara, Metro Manila, PH;
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
A wafer chip scale package (WCSP) includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads exposed by a passivation layer, and a top dielectric layer over the passivation layer. A dielectric layer bounded (DLB) cavity formed in the top dielectric layer includes a first cavity being a center through-cavity bounded by a second cavity being a partial through-cavity, the DLB cavity is lined with a seed layer. A capping dielectric layer that covers the DLB cavity except for an aperture over the first cavity. A cavity metal that is generally configured as an integral structure of continuous metal material having no interfaces is for filling the DLB cavity to form a metal filled cavity including over the aperture that has an electrical connection to the die bond pads. A solder ball over the cavity metal is positioned over the aperture.