The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Feb. 25, 2022
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

John D. Pape, Cedar Park, TX (US);

Skanda K. Srinivasa, Austin, TX (US);

Francesco Spadini, Sunset Valley, TX (US);

Brian T. Mokrzycki, Austin, TX (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/3001 (2013.01); G06F 9/30058 (2013.01); G06F 9/3016 (2013.01); G06F 9/30185 (2013.01); G06F 9/3838 (2013.01); G06F 9/3858 (2023.08); G06F 9/3861 (2013.01);
Abstract

Techniques are disclosed that relate to executing fused instructions. A processor may include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store instruction to load a value from a memory and detect a non-load/store instruction that depends on the value to be loaded. The decoder circuit may fuse the load/store instruction and the non-load/store instruction such that one or more operations that the non-load/store instruction is defined to perform are to be executed within the load/store circuit. The load/store circuit may receive an indication of the fused load/store and non-load/store instructions and then execute one or more operations of the load/store instruction and the one or more operations of the non-load/store instruction using a circuit included in the load/store circuit.


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