The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Dec. 16, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Debapriya Chatterjee, Austin, TX (US);

Brian W. Thompto, Austin, TX (US);

Jose E. Moreira, Irvington, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/74 (2013.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 21/54 (2013.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
G06F 21/74 (2013.01); G06F 9/30076 (2013.01); G06F 9/30098 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 9/3867 (2013.01); G06F 9/4812 (2013.01); G06F 21/54 (2013.01); H04L 9/0643 (2013.01); H04L 9/0894 (2013.01);
Abstract

A computer system, processor, computer program product, and method for executing instructions in a software application that includes a processor that can be dynamically controlled, in response to a value set in a control register, to operate in either a secure mode or a performance mode. In the secure mode, the processor: upon encountering a secure mode entry instruction, computes an entry hash value using a hash function and stores the entry hash value; and upon encountering a secure mode exit instruction, computes an exit hash value, loads the entry hash value, and determines whether the entry hash value is the same as the exit hash value, and depending upon verification of the hash values can execute the return function or transfer control to the operating system. In the performance mode, the processor: executes both the secure mode entry instruction and the secure mode exit instruction as no-operations.


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