Field programmable gate array-based low latency disaggregated system orchestrator

Abstract

An asynchronous computer-implemented disaggregated processing system including an ethernet transceiver configured to receive data, from a computing device over a data communications network. A core processor is configured to execute to process information associated with at least some of the received data and a memory is configured to store, via a memory controller, processed information from the core processor. A field programmable gate array is configured via an execution implementation directive to parse at least some of the received data; preprocess at least some of the parsed data for use by the core processor; route, to the core processor, the preprocessed data; receive, from the core processor, information associated with the preprocessed data; route, to the computing device, a response associated with the information associated with the preprocessed data received from the core processor; and store, via the memory controller, the information associated with the preprocessed data in the memory.