The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Mar. 28, 2023
Applicant:

Infinitum Electric, Inc., Round Rock, TX (US);

Inventors:

Edward C. Carignan, Round Rock, TX (US);

Paulo Guedes-Pinto, Round Rock, TX (US);

Assignee:

INFINITUM ELECTRIC INC., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/18 (2006.01); C25D 5/02 (2006.01); C25D 5/54 (2006.01); C25D 5/56 (2006.01); C25D 7/00 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 3/10 (2006.01);
U.S. Cl.
CPC ...
H05K 3/188 (2013.01); C25D 5/02 (2013.01); C25D 5/54 (2013.01); C25D 5/56 (2013.01); C25D 7/00 (2013.01); H05K 1/0284 (2013.01); H05K 1/0366 (2013.01); H05K 3/107 (2013.01);
Abstract

A method of manufacturing a printed circuit board (PCB) includes forming a tridimensional (3D) dielectric substrate on a fiber-reinforced polymer with opposite sides; forming each side with channels and pockets by molding dielectric laminate, and the channels and pockets define a layout for conductive traces and pads of the PCB; forming the channels and pockets in a same side of the 3D dielectric substrate at a uniform depth; forming side walls of the channels and pockets of the 3D dielectric substrate with a draft angle in a range of greater than 0 degrees to about 5 degrees; depositing by electrolytic metallization the conductive traces and pads into the channels and pockets of the 3D dielectric substrate; and the outer surface of those conductive traces and pads are flush with the sides of the 3D dielectric substrate.


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