The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2024
Filed:
Jan. 24, 2022
Chengdu Monolithic Power Systems Co., Ltd., Chengdu, CN;
Yanjie Lian, Chengdu, CN;
Chengdu Monolithic Power Systems Co., Ltd., Sichuan, CN;
Abstract
An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion, the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer.