The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Aug. 02, 2019
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Hajime Yamagishi, Kanagawa, JP;

Eiji Sato, Kanagawa, JP;

Akira Yamazaki, Kanagawa, JP;

Takayuki Sekihara, Kanagawa, JP;

Makoto Hayafuchi, Kanagawa, JP;

Syunsuke Ishizaki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 27/14636 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/08146 (2013.01);
Abstract

Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.


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