The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2024

Filed:

Nov. 10, 2021
Applicant:

Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

Weilin Wang, Beijing, CN;

Xiaoliang Kang, Shaanxi Province, CN;

Xuemin Zhang, Shanghai, CN;

Chen Chen, Beijing, CN;

Yang Shi, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 1/3234 (2019.01); G06F 9/4401 (2018.01); G06F 9/48 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01); H04L 1/00 (2006.01); H04L 45/00 (2022.01); H04L 45/02 (2022.01); H04L 45/42 (2022.01); H04L 45/745 (2022.01); H04L 69/324 (2022.01);
U.S. Cl.
CPC ...
G06F 13/4265 (2013.01); G06F 1/3234 (2013.01); G06F 9/4418 (2013.01); G06F 9/4812 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); G06F 13/4068 (2013.01); G06F 15/7807 (2013.01); G06F 15/7825 (2013.01); H04L 1/004 (2013.01); H04L 45/02 (2013.01); H04L 45/22 (2013.01); H04L 45/42 (2013.01); H04L 45/745 (2013.01); H04L 69/324 (2013.01); G06F 13/4208 (2013.01); G06F 13/4282 (2013.01);
Abstract

A interconnect system, including a plurality of sockets and a first interconnect interface. Any two of the sockets are accessible to each other's hardware resources by transmitting a first packet and a second packet through the first interconnect interface. The first packet includes first interconnect information, used for establishing communication between the two sockets. The second packet includes a first data payload, loaded from one of the two sockets. The sockets include a first socket and a second socket, configured to be interconnected with each other through the first interconnect interface.


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