The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Mar. 24, 2020
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Li Liu, Beijing, CN;

Pengcheng Lu, Beijing, CN;

Rongrong Shi, Beijing, CN;

Yuanlan Tian, Beijing, CN;

Xiao Bai, Beijing, CN;

Dacheng Zhang, Beijing, CN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02);
Abstract

Provided is display substrate, including driving circuit board, and first electrode layer, insulating layer, second electrode layer, isolation layer, transparent conductive layer sequentially stacked thereon. Driving circuit board includes pixel and bonding regions. First electrode layer includes first sub-portion in bonding region and second sub-portion in pixel region. Insulating and isolation layers are partially cover bonding and pixel regions. Insulating layer has first via hole in area corresponding to first sub-portion. Isolation layer has second via hole in the area. Axes of first and second via holes coincide, first sub-portion is exposed at first and second via holes. Second electrode layer is in pixel region, coupled to second sub-portion through third via hole in area corresponding to second sub-portion. Isolation layer has fourth via hole in area corresponding to second electrode layer. Transparent conductive layer is in pixel region, coupled to second electrode layer through fourth via hole.


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