The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Sep. 24, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Daniel Jacob Benjamin Bechstein, Pacifica, CA (US);

MohammadAli Khorrami, San Jose, CA (US);

Vipin Ayanoor-Vitikkate, Pleasanton, CA (US);

Blake R. Marshall, San Jose, CA (US);

Zhibin Wang, San Jose, CA (US);

Ying Cao, Santa Clara, CA (US);

Robert Ubo Liu, San Jose, CA (US);

John Stephen Smith, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05F 3/00 (2006.01); G06F 3/0354 (2013.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
H05F 3/00 (2013.01); G06F 3/03545 (2013.01); G06F 3/0442 (2019.05); G06F 3/0446 (2019.05);
Abstract

An electrostatic discharge (ESD) robust design for an input device such as a stylus is disclosed. The input device can include one or more components, such as one or more Schottky diodes, that can be damaged by ESD events. To reduce the likelihood of damage to sensitive components, the parasitic capacitance between sensitive conductive paths and reference ground paths of the input device that could otherwise provide electrostatic discharge paths can be reduced (arranging current limiting resistance at specific locations among sensitive components, creating physical separation between sensitive conductive paths and reference ground paths), shielding can be added to shield the sensitive electronics from ESD pulses, and high dielectric breakdown material can be added to prevent ESD pulse entry or exit of not otherwise protected circuit parts.


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