The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Apr. 10, 2023
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Koshun Saito, Kyoto, JP;

Hiroyuki Sakairi, Kyoto, JP;

Yasufumi Matsuoka, Kyoto, JP;

Kenichi Yoshimochi, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/49503 (2013.01); H01L 23/4952 (2013.01); H01L 23/49562 (2013.01); H01L 24/48 (2013.01); H01L 2224/48245 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/1067 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/30101 (2013.01); H01L 2924/30107 (2013.01);
Abstract

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.


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