The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Aug. 16, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Woosung Yang, Gwangmyeong-si, KR;

Jiyoung Kim, Hwaseong-si, KR;

Jiwon Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H10B 43/27 (2023.02);
Abstract

A semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A supporter is on the horizontal conductive layer. The supporter includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection mold layer is between the third portion and the horizontal conductive layer. A first buried insulation layer passing through the third portion, the connection mold layer, and the horizontal conductive layer is provided. A stacked structure is on the substrate. A through electrode passing through the first buried insulation layer is provided.


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