The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

May. 17, 2022
Applicant:

AU Optronics Corporation, Hsin-Chu, TW;

Inventors:

Hsiang-Chi Cheng, Hsin-Chu, TW;

Shyh-Bin Kuo, Hsin-Chu, TW;

Yi-Cheng Lai, Hsin-Chu, TW;

Chung-Hung Chen, Hsin-Chu, TW;

Shih-Hsien Yang, Hsin-Chu, TW;

Yu-Chih Wang, Hsin-Chu, TW;

Kuo-Hsiang Chen, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G11C 8/08 (2006.01); G11C 8/18 (2006.01);
U.S. Cl.
CPC ...
G11C 8/10 (2013.01); G11C 8/08 (2013.01); G11C 8/18 (2013.01);
Abstract

A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.


Find Patent Forward Citations

Loading…