The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

May. 16, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Kosuke Yanagidaira, Fujisawa Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); H01L 25/065 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1verification operation is ended after a kverification operation is ended in the nwrite loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nwrite loop is supplied to the word line before start of the k+1verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1verification operation is shorter than a time from start of the first verification operation to end of the kverification operation in the nwrite loop.


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