The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2024
Filed:
Mar. 30, 2022
Applicant:
Beijing Vcore Technology Co., Ltd., Beijing, CN;
Inventors:
Jiye Zhao, Beijing, CN;
Dandan Huan, Beijing, CN;
Assignee:
BEIJING VCORE TECHNOLOGY CO., LTD., Beijing, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G06F 12/0811 (2016.01); G06F 12/0817 (2016.01); G06F 12/128 (2016.01); G11C 5/04 (2006.01); G11C 11/406 (2006.01);
U.S. Cl.
CPC ...
G06F 12/128 (2013.01); G06F 12/0811 (2013.01); G06F 12/082 (2013.01); G11C 5/04 (2013.01); G06F 2212/621 (2013.01); G11C 11/40618 (2013.01); G11C 11/40626 (2013.01); G11C 2211/4061 (2013.01);
Abstract
A SEDRAM-based stacked Cache system is integrated in multiple layers of wafers bonded together and includes a Cache, a Cache controller and a SEDRAM controller; the multiple layers of wafers includes a SEDRAM wafer structure and a processor wafer structure; a SEDRAM unit is integrated in each layer of SEDRAM wafer in the SEDRAM wafer structure and configured as a storage space of the Cache; a CPU, the Cache controller, the SEDRAM controller and a memory controller are integrated in the processor wafer structure.