The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Apr. 09, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Hiroyuki Tanaka, Yokkaichi, JP;

Hiroyuki Ogawa, Nagoya, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02);
Abstract

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, and memory stack structures vertically extending through a respective one of the alternating stacks and located within the first memory array region and the second memory array region. An inter-array region containing lower and upper staircases is located between the first and the second memory array regions. The first memory array region may have a greater length than the second memory array region, or the lower staircase may generally ascend in an opposite direction from the upper staircase.


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