The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Mar. 25, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Michael Stadler, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/0807 (2013.01); H01L 2224/32145 (2013.01);
Abstract

A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.


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