The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Mar. 01, 2022
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventor:

Toshiaki Dozaka, Yokohama Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01); H01L 27/02 (2006.01); H02H 9/04 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); H01L 27/0266 (2013.01); H01L 27/0288 (2013.01); H01L 27/0292 (2013.01); H02H 9/045 (2013.01); G11C 17/16 (2013.01);
Abstract

According to one embodiment, an integrated circuit includes a first power supply line, a protection circuit, an internal circuit, a second transistor, and a shutoff control circuit. A first power supply voltage is supplied to the first power supply line. The protection circuit is connected to the first power supply line. The internal circuit includes a first transistor whose breakdown voltage is lower than the first power supply voltage. A drain or a source of the first transistor is connected to the first power supply line. The second transistor is on the first power supply line between the protection circuit and the internal circuit and is configured to switch between conduction and non-conduction states to connect and disconnect the protection circuit and the internal circuit from one another along the first power supply line. The shutoff control circuit is configured to turn off the second transistor during an ESD operation.


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