The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2024

Filed:

Dec. 29, 2021
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Anwar Kashem, Boxborough, MA (US);

Craig Daniel Eaton, Austin, TX (US);

Pouya Najafi Ashtiani, Munich, DE;

Deepesh John, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); H03K 5/22 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); H03K 5/22 (2013.01); H03K 2005/00286 (2013.01);
Abstract

Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.


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