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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11985857 B1

PDFFull Text
Date of Patent:
May. 14, 2024

Filed:

May. 12, 2023

Display device, method of manufacturing display device, and electronic apparatus

Applicant:

Sony Group Corporation, Tokyo, JP;

Inventor:

Hitoshi Tsuno, Kanagawa, JP;

Assignee:

Sony Group Corporation, Tokyo, JP;

Attorney:

Michael Best & Friedrich LLP

Primary Examiner:

Laura M Menz

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/28 (2006.01); H01L 21/66 (2006.01); H01L 27/12 (2006.01); H01L 29/41 (2006.01); H01L 29/786 (2006.01); H01L 29/788 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H01L 21/28 (2013.01); H01L 22/20 (2013.01); H01L 27/1251 (2013.01); H01L 29/41 (2013.01); H01L 29/786 (2013.01); H01L 29/78645 (2013.01); H01L 29/78648 (2013.01); H01L 29/788 (2013.01); H10K 59/131 (2023.02); H01L 21/26513 (2013.01); H01L 21/28556 (2013.01); H01L 27/124 (2013.01); H01L 27/1274 (2013.01); H10K 59/1201 (2023.02);
Abstract

A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. Agate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

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