The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Jul. 18, 2022
Applicant:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Inventors:

Yuniarto Widjaja, San Jose, CA (US);

Jin-Woo Han, San Jose, CA (US);

Benjamin S. Louie, Fremont, CA (US);

Assignee:

Zeno Semiconductor, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/404 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01); H01L 29/70 (2006.01); H01L 29/73 (2006.01); H01L 29/732 (2006.01); H01L 29/78 (2006.01); H10B 12/10 (2023.01); H10B 41/35 (2023.01);
U.S. Cl.
CPC ...
H10B 12/20 (2023.02); G11C 11/404 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3427 (2013.01); H01L 29/0804 (2013.01); H01L 29/0821 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/70 (2013.01); H01L 29/73 (2013.01); H01L 29/7302 (2013.01); H01L 29/7841 (2013.01); H10B 12/10 (2023.02); H10B 41/35 (2023.02); H01L 29/1004 (2013.01); H01L 29/732 (2013.01);
Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.


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