The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

May. 25, 2023
Applicant:

Sigmasense, Llc., Wilmington, DE (US);

Inventors:

Grant Howard McGibney, Calgary, CA;

Patrick Troy Gray, Cedar Park, TX (US);

Gerald Dale Morrison, Redmond, WA (US);

Daniel Keith Van Ostrand, Leander, TX (US);

Assignee:

SIGMASENSE, LLC., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); G06F 3/041 (2006.01); G06F 3/044 (2006.01); H03H 7/01 (2006.01); H03M 1/12 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0626 (2013.01); G06F 3/044 (2013.01); H03H 7/0161 (2013.01); H03M 1/1245 (2013.01); H03M 3/462 (2013.01); G06F 3/041 (2013.01);
Abstract

A digital decimation filtering circuit of an analog to digital conversion circuit includes an n-tap anti-aliasing filter operable to receive a 1-bit analog to digital converter (ADC) output signal at an oversampling rate and filter the 1-bit ADC output signal to remove frequencies higher than a selected cut-off frequency to produce an n-bit filtered signal at a first data output rate. The digital decimation filtering circuit further includes a decimator operable to receive the n-bit filtered signal at the first data output rate, decimate the n-bit filtered signal by a decimation factor to produce a set of output signals, and sum the set of outputs to produce a decimated signal at a second data output rate. The first data output rate is greater than the second data output rate.


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