Hybrid field-effect transistor

Abstract

The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths. In one example, the center of the channel away from the edges has a first doping concentration of a first conductivity type, and the sides of the channel along the channel edges have a second doping concentration of the first conductivity type, where the second doping concentration is greater than the first doping concentration. In another example, the dielectric layer is thicker over the sides of the channel and thinner over the center of the channel. In another example, regions of the substrate below the sides of the channel have a higher doping concentration than a region of the substrate below the center of the channel. In some examples, the FET structure has both the dielectric layer of different thicknesses and the different doping concentrations in the channel and/or the substrate.