The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

May. 09, 2023
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Kentaro Kawai, Tokyo, JP;

Yuuji Oomori, Tokyo, JP;

Yoshihide Ohue, Tokyo, JP;

Assignee:

JAPAN DISPLAY INC., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1334 (2006.01); G02F 1/1335 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/133357 (2021.01); G02F 1/133388 (2021.01); G02F 1/13347 (2021.01); G02F 1/133512 (2013.01); G02F 1/136286 (2013.01); G02F 2202/16 (2013.01);
Abstract

The display device has a first substrate having a display area including pixels and a peripheral area surrounding the display area and including a peripheral circuit, a second substrate arranged facing the first substrate, a liquid crystal layer arranged between the first substrate and the second substrate, and a plurality of gate wirings spaced apart in a first direction in the peripheral circuit of the first substrate, and a plurality of signal lines spaced apart in a second direction intersecting the first direction, wherein the second substrate has a black matrix with a lattice area at a position facing the display area and the peripheral circuit, and the lattice area of the black matrix is arranged to overlap the plurality of gate wirings and the plurality of signal lines of the peripheral circuit.


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