The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2024
Filed:
Jan. 29, 2021
Boe Technology Group Co., Ltd., Beijing, CN;
Jiguo Wang, Beijing, CN;
Jian Sun, Beijing, CN;
Zhao Zhang, Beijing, CN;
Liang Tian, Beijing, CN;
Weida Qin, Beijing, CN;
Zhen Wang, Beijing, CN;
Han Zhang, Beijing, CN;
Wenwen Qin, Beijing, CN;
Xiaoyan Yang, Beijing, CN;
Yue Shan, Beijing, CN;
Wei Yan, Beijing, CN;
Jian Zhang, Beijing, CN;
Deshuai Wang, Beijing, CN;
Yadong Zhang, Beijing, CN;
Jiantao Liu, Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
Abstract
An array substrate includes: a first substrate (), including a plurality of sub-pixel regions () arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (), provided with a first via hole () located in the sub-pixel regions (), and includes at least one pattern portion (), the pattern portion () includes a plurality of pattern units () arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes () that are mutually disconnected, each of the reflective electrodes () is located in one of the sub-pixel regions () and is electrically connected to the sub-pixel circuit through the first via hole ().