The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Aug. 25, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abbas Ali, Plano, TX (US);

Christopher Scott Whitesell, Garland, TX (US);

John Christopher Shriner, Lucas, TX (US);

Henry Litzmann Edwards, Garland, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); H01L 27/088 (2013.01);
Abstract

A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.


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