Multiprocessor pipeline architecture

Abstract

Exemplary embodiments for a multiprocessor pipeline architecture that converts signals from sequencing sample acquisition into sequence data, comprising: a custom coprocessor card configured to directly receive a stream of serialized sensor data generated by an image sensor, wherein the sensor data represents frame-by-frame intensity values for pixels comprising the image sensor, wherein the image sensor captures images of light emitted from a plurality of reaction cells of a removable integrated sequencing chip; a first coprocessor that continually receives the stream of serialized sensor data and transposes the frame-by-frame intensity values into reaction cell chunks, each of the reaction cell chunks representing movie data of the pixel intensity values of a corresponding reaction cell across the frames over a predetermined time window; a buffer that repeatedly receives the reaction cell chunks and stores in contiguous memory locations the reaction cell chunks for each respective reaction cell over a larger predetermined time window to create larger reaction cell chunks; and a plurality of second coprocessors that retrieve the larger reaction cell chunks from the buffer and convert, in parallel, the pixel intensity values into base-by-base sequence data even as additional reaction cell chunks are received by the buffer, such that the second coprocessors begin raw base calling before all the sensor data for the sequencing sample acquisition is obtained. Aspects of the invention include methods for base calling using single instruction multiple data vector processing units.