The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Aug. 22, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Jaideep Dastidar, San Jose, CA (US);

David James Riddoch, Cambridgeshire, GB;

Steven Leslie Pope, Cambridge, GB;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 13/28 (2013.01);
Abstract

An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).


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