The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2024

Filed:

Oct. 04, 2022
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Jeffrey L. Kennedy, Austin, TX (US);

Timothy M. Lambert, Austin, TX (US);

Sanjiv C. Sinha, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 1/26 (2006.01); G06F 13/20 (2006.01);
U.S. Cl.
CPC ...
G06F 1/266 (2013.01); G06F 11/0745 (2013.01); G06F 11/079 (2013.01); G06F 13/20 (2013.01);
Abstract

An information handling system may include a host processor module comprising a host processor field programmable gate array, a management controller communicatively coupled to the host processor field programmable gate array and configured to provide out-of-band management facilities for management of the information handling system, and an interposer configured to interface between the host processor field programmable gate array and one or more peripheral devices in order to perform power management and control of the one or more peripheral device. The interposer may include a general purpose input/output extender configured to enable and control power delivery to the one or more peripheral devices and a microcontroller unit communicatively coupled to the host processor field programmable gate array and configured to perform monitoring and discovery of the one or more peripheral devices.


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