The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2024
Filed:
Mar. 09, 2022
Samsung Electronics Co., Ltd., Suwon-si, KR;
Youn Gon Oh, Hwaseong-si, KR;
Ji Hun Kim, Uiwang-si, KR;
Sae Yun Ko, Hwaseong-si, KR;
Gil Ho Gu, Hwaseong-si, KR;
Dong Su Kim, Hwaseong-si, KR;
Eun Hee Lee, Hwaseong-si, KR;
Ho Chan Lee, Seoul, KR;
Seong Sil Jeong, Incheon, KR;
Seong Pyo Hong, Hwaseong-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.