The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2024
Filed:
Nov. 12, 2020
Insiava (Pty) Ltd., Pretoria, ZA;
Artur Wilhelm Suntken, Pretoria, ZA;
Nicolaas Mattheus Fauré, Pretoria, ZA;
INSIAVA (PTY) LTD., , ZA;
Abstract
An electronic circuit configured to present a high-impedance load between a load point and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D) connected in parallel with the capacitive element (C), a first switching element (S) provided in series between the first node (A) and a voltage source point, a second switching element (S) provided between the first node (A) and a second node (Node B), a second element (D) connected between the second switching element (S), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S) is closed and the second switching element (S) to charge a nodal voltage v(t) at the first node (A). In discharge stage, the first switching element (S) is open and the second switching element (S) is open to enable discharging of the capacitive element (C) through the first element (D). In a transfer stage, the second switching element (S) is closed to connect the first node (A) and the second node (B), after which the second switching element (S) is opened and the second element (D) is biased to present the high-impedance load.