The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

May. 02, 2022
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Timothy Edward Boles, Tyngsboro, MA (US);

James J. Brogle, Merrimac, MA (US);

Margaret Mary Barter, Lowell, MA (US);

David Hoag, Walpole, MA (US);

Michael G. Abbott, Canton, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/868 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 23/29 (2006.01); H01L 23/535 (2006.01); H01L 23/66 (2006.01); H01L 27/06 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/868 (2013.01); H01L 21/02129 (2013.01); H01L 21/2652 (2013.01); H01L 21/3065 (2013.01); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 21/822 (2013.01); H01L 23/291 (2013.01); H01L 23/535 (2013.01); H01L 23/66 (2013.01); H01L 27/0676 (2013.01); H01L 29/045 (2013.01); H01L 29/16 (2013.01); H01L 29/6609 (2013.01); H01L 2223/6683 (2013.01);
Abstract

Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.


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