The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Apr. 03, 2023
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Junichiro Sakata, Atsugi, JP;

Toshinari Sasaki, Atsugi, JP;

Miyuki Hosoba, Isehara, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 27/1218 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/78633 (2013.01); H01L 29/78645 (2013.01); H01L 29/78648 (2013.01); H01L 29/78654 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01);
Abstract

An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.


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