The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Oct. 28, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Sang-Uk Kim, Cheonan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4807 (2013.01); H01L 21/565 (2013.01); H01L 23/3157 (2013.01); H01L 23/49866 (2013.01); H01L 23/642 (2013.01); H01L 24/08 (2013.01); H01L 24/48 (2013.01); H01L 28/40 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/48227 (2013.01);
Abstract

A semiconductor package includes a first redistribution substrate, a connection substrate on the first redistribution substrate and having a first opening and a second opening that penetrate the connection substrate, a semiconductor chip on the first redistribution substrate and in the first opening of the connection substrate, a chip module on the first redistribution substrate and in the second opening of the connection substrate, and a molding layer that covers the semiconductor chip, the chip module, and the connection substrate. The chip module includes an inner substrate and a first passive device on the inner substrate. In the second opening, the molding layer covers the first passive device on the inner substrate.


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