The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Feb. 01, 2016
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Douglas C. Burger, Bellevue, WA (US);

Aaron L. Smith, Seattle, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/26 (2006.01); G06F 9/32 (2018.01); G06F 9/345 (2018.01); G06F 9/35 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 9/52 (2006.01); G06F 11/36 (2006.01); G06F 12/0806 (2016.01); G06F 12/0862 (2016.01); G06F 12/1009 (2016.01); G06F 13/42 (2006.01); G06F 15/78 (2006.01); G06F 15/80 (2006.01); G06F 9/355 (2018.01); G06F 12/0811 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3016 (2013.01); G06F 9/268 (2013.01); G06F 9/30007 (2013.01); G06F 9/30021 (2013.01); G06F 9/30036 (2013.01); G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/3005 (2013.01); G06F 9/30058 (2013.01); G06F 9/30072 (2013.01); G06F 9/30076 (2013.01); G06F 9/30087 (2013.01); G06F 9/3009 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G06F 9/30105 (2013.01); G06F 9/30138 (2013.01); G06F 9/30145 (2013.01); G06F 9/30167 (2013.01); G06F 9/30189 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/35 (2013.01); G06F 9/3802 (2013.01); G06F 9/3804 (2013.01); G06F 9/3822 (2013.01); G06F 9/3824 (2013.01); G06F 9/3828 (2013.01); G06F 9/383 (2013.01); G06F 9/3836 (2013.01); G06F 9/3838 (2013.01); G06F 9/3842 (2013.01); G06F 9/3848 (2013.01); G06F 9/3851 (2013.01); G06F 9/3853 (2013.01); G06F 9/3856 (2023.08); G06F 9/38585 (2023.08); G06F 9/3867 (2013.01); G06F 9/3891 (2013.01); G06F 9/466 (2013.01); G06F 9/528 (2013.01); G06F 11/36 (2013.01); G06F 11/3648 (2013.01); G06F 11/3656 (2013.01); G06F 12/0806 (2013.01); G06F 12/0862 (2013.01); G06F 12/1009 (2013.01); G06F 13/4221 (2013.01); G06F 15/7867 (2013.01); G06F 15/80 (2013.01); G06F 15/8007 (2013.01); G06F 9/3013 (2013.01); G06F 9/321 (2013.01); G06F 9/355 (2013.01); G06F 9/3557 (2013.01); G06F 12/0811 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01); G06F 2212/602 (2013.01); G06F 2212/604 (2013.01); G06F 2212/62 (2013.01); Y02D 10/00 (2018.01);
Abstract

Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.


Find Patent Forward Citations

Loading…