The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Mar. 01, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Hirotsugu Kajihara, Yokohama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0613 (2013.01); G06F 3/0619 (2013.01); G06F 3/0634 (2013.01); G06F 3/0635 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01);
Abstract

According to one embodiment, a memory system includes: a plurality of memory chips; a plurality of memory controllers; and a data encoding circuit configured to form a first group including a continuous plurality of first divided data among the user data, and generate a plurality of first page data. The memory controllers adjust a schedule of a write operation among the memory controllers and control a number of the write operations to be simultaneously executed. When at least one of the memory chips is in a busy state in a first read request, the memory controller connected to the memory chip in the busy state decodes the first divided data through erasure correction decoding processing using the first divided data read from the memory chip not in the busy state.


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