The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Feb. 28, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Apoorva Bhatia, Lucknow, IN;

Pranav Kumar, Ranchi, IN;

Abhrarup Barman Roy, Bangalore, IN;

Peeyoosh Mirajkar, Bangalore, IN;

Raghavendra Reddy, Prakasam, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 1/08 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 1/08 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01);
Abstract

In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.


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