The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Aug. 19, 2020
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Tatsuya Maruyama, Tokyo, JP;

Yusaku Otsuka, Tokyo, JP;

Hidenori Omiya, Tokyo, JP;

Toshiki Shimizu, Tokyo, JP;

Iori Kobayashi, Tokyo, JP;

Kazutaka Onishi, Tokyo, JP;

Noritaka Matsumoto, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/418 (2006.01); G05B 19/042 (2006.01);
U.S. Cl.
CPC ...
G05B 19/0423 (2013.01); G05B 2219/25213 (2013.01);
Abstract

In the conventional distributed control system, since each control device updates the data area at a timing when a control packet is received, in a case where there is a difference in communication delay between the control devices or in a case where the communication delay includes jitter, it is difficult to match the contents of data in all the control devices in a case of focusing on a certain moment during system operation. Therefore, depending on the start timing of a control application, the control application operates on the basis of different data between the control devices, thus limiting control performance improvement. Accordingly, time slots on the network are allocated according to the result of a calculation unit, and a cyclic memory synchronization update unit synchronizes the timing of reflecting data in the input/output and the cyclic memory and the timing of using data of a cyclic memory.


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