The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Aug. 11, 2020
Applicant:

Nokia Solutions and Networks Oy, Espoo, FI;

Inventors:

Andrea Enrici, Bourg la Reine, FR;

Bogdan Uscumlic, Les Ulis, FR;

Julien Lallet, Lannion, FR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 43/0852 (2022.01); G06F 16/901 (2019.01); G06F 30/34 (2020.01); H04L 47/56 (2022.01); H04L 47/74 (2022.01); H04L 47/80 (2022.01); H04L 47/83 (2022.01);
U.S. Cl.
CPC ...
H04L 43/0852 (2013.01); G06F 16/9017 (2019.01); G06F 30/34 (2020.01); H04L 47/56 (2013.01); H04L 47/745 (2013.01); H04L 47/801 (2013.01); H04L 47/805 (2013.01); H04L 47/83 (2022.05);
Abstract

A method for allocating resources of a field-programmable gate array (FPGA), the method comprising: deterministically estimating a maximum latency for executing a network service at the FPGA; determining that the maximum latency is less than a threshold latency value associated with the network service; outputting an acknowledgement indicating that the maximum latency is less than or equal to the threshold latency value; receiving confirmation that the FPGA has been selected to execute the network service within a threshold time period; and deterministically scheduling the resources of the FPGA for executing the network service in response to receiving the confirmation within the threshold time period.


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