The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Jan. 13, 2021
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Harumi Tanaka, Kanagawa, JP;

Yoshiaki Masuda, Kanagawa, JP;

Shinji Miyazawa, Kanagawa, JP;

Minoru Ishida, Tokyo, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); G01N 21/64 (2006.01); G01N 21/78 (2006.01); H01L 23/48 (2006.01); H01L 31/054 (2014.01); H04N 25/48 (2023.01); H04N 25/70 (2023.01);
U.S. Cl.
CPC ...
H01L 27/14605 (2013.01); G01N 21/64 (2013.01); G01N 21/78 (2013.01); H01L 23/481 (2013.01); H01L 27/14618 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14685 (2013.01); H01L 27/14687 (2013.01); H01L 31/0543 (2014.12); H04N 25/48 (2023.01); H04N 25/70 (2023.01); G01N 21/6454 (2013.01); G01N 2021/6471 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14634 (2013.01);
Abstract

The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.


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