The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Apr. 08, 2020
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

Christian Marc Lautensack, Tuebingen, DE;

Alexander Kaiser, Schoerzingen, DE;

Jan Homoth, Reutlingen, DE;

Assignee:

ROBERT BOSCH GMBH, Stuttgart, DE;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 23/367 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 23/367 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 23/49894 (2013.01); H01L 25/18 (2013.01);
Abstract

A semiconductor power module including first and second power transistors situated in parallel between first collector and first emitter strip conductors. A first connection surface of each of the power transistors is electroconductively connected to the first collector strip conductor, and a second connection surface of each of the power transistors is electroconductively connected to the first emitter strip conductor, so that a current flowing between the first collector strip conductor and the first emitter strip conductor is divided between the power transistors when the power transistors are each conductively connected via an applied control voltage. A first external power contact is directly contacted with the first collector strip conductor at a first contact area, a second external power contact is contacted with the first emitter strip conductor at a second contact area via a first connecting element, and the second contact area is positioned asymmetrically between the power transistors.


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