The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Jun. 01, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Roel Lieve P Uytterhoeven, Heverlee, BE;

Wim Dehaene, Leuven, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H03K 3/00 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01); G06F 117/04 (2020.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H03K 3/037 (2013.01); G06F 2117/04 (2020.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01);
Abstract

An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.


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