Beamforming hardware accelerator for radar systems

Abstract

A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas. The instructions direct the processor to iteratively access a N×M range matrix indexed by N velocity bins and M antenna combinations to obtain unique X×Y range slices of the N×M range matrix, in which X is a lesser multiple of N and Y is a lesser multiple of M; iteratively access a M×S steering matrix indexed by the M antenna combinations and S hypothesis angles to obtain unique Y×Z steering vector slices of the M×S steering matrix, in which Z is a lesser multiple of S; combine the first X×Y range slice with the first Y×Z steering vector slice to form an intermediate slice, combine each subsequently accessed X×Y range slice and corresponding Y×Z steering vector slice and add the combination to the intermediate slice until a beamforming slice is formed that incorporates data for all M antenna combinations for the particular set of X velocity bins and Z hypothesis angles. An operation is then performed on the beamforming slice.