The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2024
Filed:
Jun. 13, 2022
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Younghwan Son, Hwaseong-si, KR;
Jeehoon Han, Hwaseong-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/423 (2006.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 51/20 (2023.01); H10K 19/00 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 29/41741 (2013.01); H01L 29/42344 (2013.01); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10B 43/30 (2023.02); H10B 51/20 (2023.02); H10K 19/201 (2023.02);
Abstract
Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.