The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Feb. 11, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Tatsuya Onuki, Atsugi, JP;

Yuto Yakubo, Atsugi, JP;

Seiya Saito, Atsugi, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01); G11C 5/06 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
H10B 12/00 (2023.02); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 29/24 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); G11C 5/06 (2013.01); G11C 8/08 (2013.01);
Abstract

A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.


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