The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Dec. 23, 2022
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Ki Hyun Pyun, Yongin-si, KR;

Min Young Park, Yongin-si, KR;

Jong Min Shim, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); G09G 3/32 (2016.01); H03L 7/08 (2006.01); H03L 7/089 (2006.01); H03L 7/095 (2006.01); H03L 7/099 (2006.01); H04L 7/04 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H04L 7/033 (2013.01); G09G 3/32 (2013.01); H03L 7/0807 (2013.01); H03L 7/0891 (2013.01); H03L 7/095 (2013.01); H03L 7/099 (2013.01); H04L 7/041 (2013.01); G09G 2300/0857 (2013.01); G09G 2310/027 (2013.01); G09G 2310/08 (2013.01); H03K 19/21 (2013.01);
Abstract

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.


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