The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Jul. 30, 2021
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

David M. Dahle, Fort Collins, CO (US);

Richard Martin Born, Fort Collins, CO (US);

Deepesh John, Austin, TX (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); G06F 5/08 (2006.01); H03L 7/087 (2006.01); H03L 7/195 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0814 (2013.01); G06F 5/08 (2013.01); H03L 7/087 (2013.01); H03L 7/195 (2013.01); G06F 2205/061 (2013.01);
Abstract

Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.


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