The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Oct. 06, 2021
Applicant:

Neoconix, Inc., San Jose, CA (US);

Inventors:

Woody Maynard, State College, PA (US);

Mayuresh Patki, Harrisburg, PA (US);

David Chen, Los Altos, CA (US);

Gary Hsieh, Taoyuan, TW;

Assignee:

Neoconix, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 13/24 (2006.01); H01R 12/52 (2011.01); H01R 12/57 (2011.01); H01R 12/71 (2011.01); H01R 13/6471 (2011.01); H05K 1/02 (2006.01); H05K 3/40 (2006.01); H05K 7/10 (2006.01);
U.S. Cl.
CPC ...
H01R 12/52 (2013.01); H01R 12/57 (2013.01); H01R 12/714 (2013.01); H01R 13/2407 (2013.01); H01R 13/6471 (2013.01); H05K 1/0219 (2013.01); H05K 3/4092 (2013.01); H05K 7/1069 (2013.01);
Abstract

A connector for electrically connecting to conductive structures formed on a semiconductor device includes a core including an isolation layer and signal vias and ground vias formed in the isolation layer; a first ground plane formed on a surface of or in the core and electrically connected to the ground vias; a first set of contact elements formed on a first surface of the core and electrically connected to the signal vias to form signal pins; a second set of contact elements formed on the first surface and electrically connected to a subset of the ground vias to form ground pins. The remaining ground vias without contact elements form buried ground vias. The first and second sets of contact elements are arranged on the first surface of the core to surround each signal pin by at least one adjacent ground pin and one or more adjacent buried ground vias.


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