The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2024
Filed:
Apr. 27, 2022
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Wen-Hung Lo, Saratoga, CA (US);
Michael Ivan Halfen, San Francisco, CA (US);
Abhishek Dhir, Mississauga, CA;
Jaewon Lee, Santa Clara, CA (US);
Assignee:
NVIDIA CORP., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/14 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1066 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/1093 (2013.01); G11C 7/14 (2013.01);
Abstract
A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.