Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods

Abstract

Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods. To increase memory density, the memory array has a first memory sub-bank and one or more second memory sub-banks. The first memory sub-bank includes a first bit line(s) for each of its memory column circuits. To avoid the need to extend the length of the first bit lines to be coupled to the second memory bit cells in the second memory sub-bank, each memory sub-bank has its own dedicated first and second bit lines coupling their respective memory bit cells to access circuitry. The second bit lines effectively 'fly' independent of the first bit lines of the first memory sub-bank. The first bit lines of the first memory sub-bank do not have to be extended in length to provide bit lines for the second memory sub-bank.